Design and Implementation of Neural Network in FPGA
Keywords:
Neural Network, FPGA, MatlabAbstract
This paper constructs fully parallel NN hardware architecture, FPGA has been used to reduce neuron hardware by design the activation function inside the neuron without using lookup table as in most researches, to perform an efficient NN. It consist of two main parts; the first part covers network training using MATLAB program, the second part represents the hardware implementation of the trained network through Xilinx high performance Virtex2 FPGA schematic entry design tools.
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Published
2012-09-01
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Articles
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This work is licensed under a Creative Commons Attribution 4.0 International License.
The Journal of Engineering and Sustainable Development is an open-access journal that all contents are free of charge. Articles of this journal are licensed under the terms of the Creative Commons Attribution International Public License CC-BY 4.0 (https://creativecommons.org/licenses/by/4.0/legalcode) that licensees are unrestrictly allowed to search, download, share, distribute, print, or link to the full texts of the articles, crawl them for indexing and reproduce any medium of the articles provided that they give the author(s) proper credits (citation). The journal allows the author(s) to retain the copyright of their published article.
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How to Cite
Design and Implementation of Neural Network in FPGA. (2012). Journal of Engineering and Sustainable Development, 16(3), 73-90. https://jeasd.uomustansiriyah.edu.iq/index.php/jeasd/article/view/1269
