Low Cost and High Speed Look-Up Table Implementation of Xilinx FPGA
الكلمات المفتاحية:
zeroالملخص
There are two methods to implement LUT up to 7-bit depends on the type of Xilinx chip hardware and the software that can use in design and the code generation. The first method implements LUT as a RAM. This method gives high speed and requires a very high cost.The second method implements LUT as logic gates. This method requires special software and gives a low speed implies. This paper proposed a modification to the second method that will save the speed of the first method and low cost of the second method. It depends on the design of the LUT. Therefore it will not require special software.
التنزيلات
Key Dates
منشور
2005-06-01
إصدار
القسم
Articles
الرخصة
هذا العمل مرخص بموجب Creative Commons Attribution 4.0 International License.
The Journal of Engineering and Sustainable Development is an open-access journal that all contents are free of charge. Articles of this journal are licensed under the terms of the Creative Commons Attribution International Public License CC-BY 4.0 (https://creativecommons.org/licenses/by/4.0/legalcode) that licensees are unrestrictly allowed to search, download, share, distribute, print, or link to the full texts of the articles, crawl them for indexing and reproduce any medium of the articles provided that they give the author(s) proper credits (citation). The journal allows the author(s) to retain the copyright of their published article.
Creative Commons-Attribution (BY) 
كيفية الاقتباس
R. Zaghar, D. ., A. Zidan, K. ., & Laiyth M. Al-Rawi. (2005). Low Cost and High Speed Look-Up Table Implementation of Xilinx FPGA. مجلة الهندسة والتنمية المستدامة, 9(2), 16-26. https://jeasd.uomustansiriyah.edu.iq/index.php/jeasd/article/view/1848
