Design and Implementation of JPEG 2000 Image Compression using FPGA

المؤلفون

  • Munther N. B. Al-Tikriti Computer & Software Eng. Dept., College of Eng., Al-Mustansiriya University, Baghdad, Iraq مؤلف
  • Dhafer R. Z. Al-Rawi Computer & Software Eng. Dept., College of Eng. Al-Mustansiriya University, Baghdad, Iraq مؤلف
  • Ienas F. Y. Iskander Maintenance and Engineering Department, Ministry of Health, Baghdad, Iraq مؤلف

الكلمات المفتاحية:

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الملخص

This paper investigates the use of a Field Programmable Gate Array (FPGA Xilinx Virtex-II) to perform hardware implementation for low speed part of JPEG2000 to achieve a real time JPEG2000 system. In this paper multi processes modules written in the VHDL is proposed that can be used to accelerate an existing software implementation of JPEG2000.

التنزيلات

Key Dates

منشور

2006-06-01

إصدار

مجلد 10 عدد 2 (2006): Journal of Engineering and Development

القسم

Articles

الرخصة

Creative Commons License

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Creative Commons-Attribution (BY)

كيفية الاقتباس

N. B. Al-Tikriti, M. ., R. Z. Al-Rawi, D. ., & F. Y. Iskander, I. . (2006). Design and Implementation of JPEG 2000 Image Compression using FPGA. مجلة الهندسة والتنمية المستدامة, 10(2), 151-162. https://jeasd.uomustansiriyah.edu.iq/index.php/jeasd/article/view/1811