Design and Implementation of JPEG 2000 Image Compression using FPGA

Authors

  • Munther N. B. Al-Tikriti Computer & Software Eng. Dept., College of Eng., Al-Mustansiriya University, Baghdad, Iraq Author
  • Dhafer R. Z. Al-Rawi Computer & Software Eng. Dept., College of Eng. Al-Mustansiriya University, Baghdad, Iraq Author
  • Ienas F. Y. Iskander Maintenance and Engineering Department, Ministry of Health, Baghdad, Iraq Author

Keywords:

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Abstract

This paper investigates the use of a Field Programmable Gate Array (FPGA Xilinx Virtex-II) to perform hardware implementation for low speed part of JPEG2000 to achieve a real time JPEG2000 system. In this paper multi processes modules written in the VHDL is proposed that can be used to accelerate an existing software implementation of JPEG2000.

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Key Dates

Published

2006-06-01

Issue

Vol. 10 No. 2 (2006): Journal of Engineering and Development

Section

Articles

License

Creative Commons License

This work is licensed under a Creative Commons Attribution 4.0 International License.

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How to Cite

Design and Implementation of JPEG 2000 Image Compression using FPGA. (2006). Journal of Engineering and Sustainable Development, 10(2), 151-162. https://jeasd.uomustansiriyah.edu.iq/index.php/jeasd/article/view/1811