FPGA Implementation of Parallel and Pipelined Turbo Encoder for Real -Time Applications

الملخص

The main keywords defining the quality of communication system are the data rate and the data transmission reliability. Error correcting codes are generally employed to achieve the reliability of the data transmission. The present trend is to achieve high data rates on low-cost designs (such as FPGAs), especially in real time application including multimedia transmission. Most of the time, parallel, architectures are required to process error correcting codes with high data throughput.
In this paper, an effective parallel architecture is proposed for the classical Turbo encoder based on parallel and pipelining designing of RSC encoder and the implementation of interleaver using register file. The simulation results shows that the data rates up to 142.918 M bits/s can be achieved on FPGA implementations