FPGA Implementation of Multilayer Perceptron for Speech Recognition

Abstract

In this paper, a method for designing and implementing Multilayer Perceptron (MLP) based on the BP algorithm has been suggested. The method has described an MLP on Register Transfer Level (RTL) using VHDL description language and implemented on Field Programmable Gate Array (FPGA) for speech recognition. Firstly, a multiply-accumulate (MAC) unit and sigmoid nonlinear function are implemented as basic building units of the MLP. The MLP is trained by the BP learning algorithm. The optimized parameters are obtained by Matlab simulation for off-chip training design. The implementations have been developed and tested on Xilinx Spartan-IIIE XC3S500E FPGA chip for embedded systems using Xilinx ISE 10.1 software. The research also presents a summary of the performance cost and data throughput with regard to the speed and required computational resources. The proposed hardware architecture is found to be 6 times faster than the software implementation.