Design and Implementation of a TM-CFAR Processor using Field Programmable Gate Array (FPGA)

Abstract

This paper proposes on a project whose aim is to implement architectures for Constant False Alarm Rate (CFAR) processor employed in radars. These proposed architectures are implemented by using Field Programmable Gate Array (FPGA) technique, with observance of feature desired as flexibility, and speed without performance loss. This design written in VHSIC Hardware Description Language (VHDL).FPGA architecture of TM-CFAR processor is implemented to overcome the large processing time required in case of multi-target environment. The use of this technology is suitable because it offers high flexibility in modifying and even developing the required design with a reduction in the required number of hardware and cost.In addition to the main features of the processing chain architectures such as degree of parallelism, small size, accuracy and high computational speed, there is a requirement for generality and adaptively i.e. the ability to handle many different models of operation in different environments.The implementation of the design is achieved using Xilinx Virtex-II platform as a suitable selected programmable device. The development of the system software for this work has been done using Active HDL 3.5, and ISE Navigator 6.3i programs